The applicant claims and requests a foreign priority, through the Paris Convention for the Protection of Industry Property, based on a patent application filed in the Republic of Korea (South Korea) with the filing date of Jul. 5, 2000, with the patent application number 2000-0038161, by the applicant. (See the Attached Declaration)
1. Field of the Invention
The present invention relates to a central processing unit (CPU) for easily testing and debugging programs, and more particularly, to a CPU for easily testing and debugging programs in which testing and debugging application programs that have been downloaded from a host computer at a debugging state can be easily tested and debugged.
2. Description of Prior Art
In general, a CPU or a microprocessor reads a program made of a set of a plurality of instruction words stored in a memory, parses the instruction words by an instruction parser and executes an operation corresponding to each instruction word by an execution unit.
It should be tested whether an application program made of a set of the plurality of instruction words stored in a memory is correctly made up. In the case that an application program is not correctly made up, the application program should be debugged.
FIG. 1 is a block diagram showing an example for testing and debugging application programs by using a conventional in-circuit emulator.
A system for testing and debugging programs using an in-circuit emulator includes an object system 4 having a CPU module 3, an input/output (I/O) unit 1 and a memory 2, an in-circuit emulator (ICE) 5 connected to the CPU module 3 by which has replaced the CPU in the object system 4, in which the CPU in the object system 4 is replaced with the CPU module 3 in order to test and debug the object system 4, and a host computer 6 outputting instructions for testing and debugging application programs for debugging to an in-circuit emulator.
The in-circuit emulator 5 receives an application program from the host computer 6 and stores a debugging program capable of debugging the application program, and activates a central processing unit (CPU) that is located in the in-circuit emulator according to a command input from the host computer 6. Also, the in-circuit emulator 5 directly controls a control bus, an address bus and a data bus that are located in the object system 4 through the CPU module 3, in order to perform an input/output operation necessary for an input/output unit 2 and a memory 2. Also, the in-circuit emulator 5 can read an inner register of the CPU within the in-circuit emulator 5 or alter data in the inner register.
That is, the in-circuit emulator 5 receives the debugging application program from the host computer, runs the program, and operates the CPU within the in-circuit emulator 5. Also, the in-circuit emulator 5 directly controls a control bus, an address bus and a data bus that are located in the object system 4 through the CPU module 3, in order to perform an input/output operation necessary for the input/output unit 2 and the memory 2, and stops running of the application program compulsively in order to test and debug the application program. Then, data is read or written with respect to the input/output unit 1 and the memory 2 in the object system 4, or data stored in the register within the in-circuit emulator 5 is read or written, according to the command from the host computer 6. Accordingly, it is judged whether the application program is correctly made up. If there is an error, the application program is debugged.
The in-circuit emulator 5 can be useful only in the case that the CPU in the object system can be replaced with the CPU module 3 connected to the in-circuit emulator 5, when the application program is tested and debugged using the conventional in-circuit emulator. Also, since a hardware unit functioning as the CPU of the object system should exist in the in-circuit emulator 5, it is problematic that the in-circuit emulator is highly expensive. Also, since the CPU located within the in-circuit emulator cannot be replaced with the CPU module 3 in the case that the object system is integrated with a single semiconductor chip, the in-circuit emulator cannot be used.
FIG. 2 is a block diagram showing a device showing a device for testing and debugging a program in which a serial communications unit 12 and a background debugging monitor 11 are incorporated in a conventional central processing unit (CPU) 13.
Referring to FIG. 2, the CPU 13 includes the background debugging monitor (DBM) 11 and the serial communications unit 12, in order to solve the problem that the in-circuit emulator cannot be used in the case that the object system of FIG. 1 has been integrated into a single semiconductor chip.
The FIG. 2 device includes the object system 10 in which the CPU 13 having the BDM 11 and the serial communications unit 12, the input/output (I/O) unit 14 and the memory 15 are integrated into a single semiconductor chip, and a host computer 20 for testing and debugging an application program via the serial communications unit 12.
The BDM 11 should be able to directly control all internal elements located in the CPU 13, with a controller including a register and a control unit, in order to parse a command input via the serial communications unit 12 from the host computer 20, to thereby perform necessary operations. That is, the BDM 11 is connected to an internal bus to read or alter the value stored in the register. The BDM 11 controls a controller, a memory address register, and a memory data register, to thereby control a control signal bus, an address bus and a data bus, which are not shown in FIG. 2.
In the CPU including the conventional BDM as shown in FIG. 2, the host computer 20 should communicate with the BDM 11 via the serial communications unit 12. In this case, the required number of the input/output lines for connecting the host computer 20 and the CPU 13 is two or three. Accordingly, the testing and debugging device of FIG. 2 is more efficient than the case that the whole CPU is replaced as show in FIG. 1.
However, since the conventional BDM 11 should directly control all the internal elements in the CPU 13, the CPU incorporated with the BDM of FIG. 2 is expensive and has a complicated hardware device.
To solve the prior art problems, it is an object of the present invention to provide a central processing unit (CPU) facilitating a program testing and debugging operation, in which a debugging mode is newly added in the CPU having a user mode by activating a debugging input signal and an application program for testing and debugging downloaded from a host computer at the debugging mode is easily tested and debugged, to thereby simplify hardware of the CPU to lower price of the CPU and perform a more efficient testing and debugging operation.
To accomplish the above object of the present invention, according to the present invention, there is provided a central processing unit (CPU) for easily testing and debugging a program, the CPU comprising: a data communications unit for performing data communications with a host computer; a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state; a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program; and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.
According to another aspect of the present invention, there is provided a central processing unit (CPU) for easily testing and debugging a program, the CPU comprising: a data communications unit for performing data communications with a host computer; a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state; a debugging stack pointer register designating a stack memory storing data of a debugging initialization program and data of a debugging service program; a control unit for initializing the CPU by a rest signal, checking a debugging mode proceeding signal, loading a start address for performing a debugging initializing program in a program counter if the debugging mode proceeding signal has been activated, to thereby converting the CPU into the debugging initialization mode, and setting the flag of the status register into a value representing the debugging mode, and outputting various control signals necessary for internal and external components of the CPU connected to an internal bus; and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging service mode, a start address for performing a debugging service program is loaded in a program counter, and the debugging service program is executed to perform a debugging according to a command from the host computer via the data communications unit.